Tools: Topology2: Add DC block component #8145
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@ranj063 @kv2019i @plbossart I wonder if this is a good way to create simple topologies to allow test run for any processing component that can fit the one sourcec one sink template? Can it be done more efficiently with tplg2 syntax? I'd like to run these same topologies in DUT, SOF ALSA plugin, and testbench environments. |
tools/topology/topology2/include/components/dcblock/default.conf
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| @@ -0,0 +1,12 @@ | |||
| # Exported with script example_dcblock.m 27-Sep-2023 | |||
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but what about the cmd line args used to generate this and other blobs ? i.e. how would someone else reproduce this ?
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That is all needed, there are no command line args.
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Though I guess you meant how to launch the blobs generator from shell command line. I can add that as well.
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It would be then cd tools/tune/dcblock; octave --no-window-system example_dcblock.m .
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The script PR #8283 includes this change. I'd like to propose for HDA generic analog capture replace IIR with smaller MCPS dcblock so I created a set of blobs to use for the purpose there.
| exit 1 | ||
| fi | ||
| comp=$1 | ||
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| FULL_CMD=( "$0" "$@" ) |
| fn=${comp}_${format}.conf | ||
| echo Creating file "$fn" | ||
| cat > "$fn" <<EOF_COMP | ||
| # Created with script "$0 $comp" |
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| # Created with script "$0 $comp" | |
| # Created with script ${FULL_CMD[@]} |
This addresses @lgirdwood 's concern.
It does not "re-quote" whitespace but good enough for now.
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Thanks, yes that's better, though it's not same as what Liam asked.
This patch adds the widget class dcblock and a sample bytes configuration blobs. Signed-off-by: Seppo Ingalsuo <[email protected]>
This patch uses cavs-benchmark-hda.conf to build topologies to test components in a simple playback and capture configuration. host copier --> component --> DAI copier host copier <-- component <-- DAI copier The built topologies are sof-hda-benchmark-dcblock16/24/32-tgl.tplg The shell script bench_comp_generate.sh is added to conveniently generate include files needed to build new test topologies for component with s16/s24/s32 format. Signed-off-by: Seppo Ingalsuo <[email protected]>
This patch adds DRC test topologies build. Signed-off-by: Seppo Ingalsuo <[email protected]>
This patch adds IIR EQ topologies build. Signed-off-by: Seppo Ingalsuo <[email protected]>
This patch adds FIR EQ topologies build. Signed-off-by: Seppo Ingalsuo <[email protected]>
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| echo "Usage: $0 <component>" | ||
| exit 1 | ||
| fi | ||
| comp=$1 |
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Nit
| comp=$1 | |
| COMP=$1 |
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@ranj063 Good to go? |
Updated description - this is more a collection of patches to create in simple way topologies to test all processing components by e.g. loading and unloading the component & format specific topologies.
Example of topology to test s32 format dcblock: